Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG24 |
| Lead Count (#): | 24 |
| Pkg. Dimensions (mm): | 4.0 x 4.0 x 0.9 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 24 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Advanced Features | Programmable Clock, Reference Output, Spread Spectrum |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3 |
| Architecture | Common |
| C-C Jitter Typ P-P (ps) | 50 |
| Core Voltage (V) | 3.3V |
| Diff. Output Signaling | LP-HCSL, LVDS, LVPECL, LVCMOS |
| Diff. Outputs | 2 |
| Family Name | VersaClock 3S |
| Function | Generator |
| Input Freq (MHz) | 1 - 160 |
| Input Type | Crystal, LVCMOS, LVPECL, LVDS, LP-HCSL |
| Inputs (#) | 1 |
| Length (mm) | 4 |
| Longevity | 2040 Apr |
| MOQ | 490 |
| NXP Processor Function | Memory Clock, SerDes Clock, CPU/USB/Eth Clock |
| Output Banks (#) | 5 |
| Output Freq Range (MHz) | 0.032768 - 500 |
| Output Impedance | 100 |
| Output Type | LVCMOS, LVPECL, LP-HCSL, LVDS |
| Output Voltage (V) | 1.8V, 2.5V, 3.3V |
| Outputs (#) | 7 |
| Package Area (mm²) | 16 |
| Phase Jitter Typ RMS (ps) | 3 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Power Consumption Typ (mW) | 50 |
| Prog. Clock | Yes |
| Prog. Interface | I2C, OTP |
| Published | No |
| Reference Output | Yes |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| Width (mm) | 4 |
| Xtal Freq (MHz) | 8 - 40 |
| Xtal Inputs (#) | 1 |
Resources for 5P35023
Description
The 5P35023 is a VersaClock® programmable clock generator designed for low-power, consumer, and high-performance PCI Express applications. The 5P35023 device is a three-PLL architecture design, and each PLL is individually programmable and allows for up to five unique frequency outputs. The 5P35023 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshot Reduction Technology (ORT), and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after powering up, and then program the 5P35023 again through the I2C interface.
The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization based on the application requirements. It also supports three single-ended outputs and two pairs of differential outputs that support LVCMOS, LVPECL, LVDS, and LPHCSL. A low-power 32.768kHz clock is supported with only less than 5μA current consumption for the system RTC reference clock.