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PECL/CMOS to CMOS Clock Driver

Package Information

CAD Model: View CAD Model
Pkg. Type: TSSOP
Pkg. Code: PGG16
Lead Count (#): 16
Pkg. Dimensions (mm): 5.0 x 4.4 x 1.0
Pitch (mm): 0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

Product Attributes

Lead Count (#) 16
Carrier Type Tube
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 0
Qty. per Carrier (#) 96
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) 0 to 70°C
Core Voltage (V) 3.3V, 5V
Divider Value 1, 2, 3, 4
Function Buffer, Multiplexer, Divider
Input Freq (MHz) 250
Input Type LVCMOS, LVPECL
Inputs (#) 2
Length (mm) 5
MOQ 192
Output Banks (#) 2
Output Freq Range (MHz) 250
Output Skew (ps) 250
Output Type LVCMOS
Output Voltage (V) 2.5V, 3.3V, 5V
Outputs (#) 4
Package Area (mm²) 22
Pitch (mm) 0.65
Pkg. Dimensions (mm) 5.0 x 4.4 x 1.0
Pkg. Type TSSOP
Published No
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel No
Thickness (mm) 1
Width (mm) 4.4

Description

The 558-01 accepts a high speed input of either PECL or CMOS, integrates a divider of 1, 2, 3, or 4, and provides four CMOS low skew outputs. The chip also has output enables so that one, three, or all four outputs can be tri-stated. The 558-01 is a member of the IDT Clock Blocks™ family of clock generation, synchronization, and distribution devices.