Skip to main content
PECL Input Oscar™ User Configurable Clock

Package Information

CAD Model: View CAD Model
Pkg. Type: QSOP
Pkg. Code: PCG28
Lead Count (#): 28
Pkg. Dimensions (mm): 9.9 x 3.8 x 1.47
Pitch (mm): 0.64

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

Product Attributes

Lead Count (#) 28
Carrier Type Tube
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 0
Qty. per Carrier (#) 48
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) -40 to 85°C
Core Voltage (V) 3.3V, 5V
Feedback Input No
Input Freq (MHz) 0.5 - 250
Input Type LVPECL
Inputs (#) 1
Length (mm) 9.9
MOQ 144
Output Banks (#) 1
Output Freq Range (MHz) 1 - 250
Output Type LVCMOS, LVPECL
Output Voltage (V) 3.3V, 5V
Outputs (#) 2
Package Area (mm²) 37.6
Period Jitter Typ P-P (ps) 350
Pitch (mm) 0.64
Pkg. Dimensions (mm) 9.9 x 3.8 x 1.47
Pkg. Type QSOP
Prog. Clock No
Published No
Reference Output No
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Spread Spectrum No
Tape & Reel No
Thickness (mm) 1.47
Width (mm) 3.8

Description

The 525-03 are the most flexible way to generate a high-quality, high-accuracy, high-frequency clock output from a PECL input. The name OSCaR stands for OSCillator Replacement, as they are designed to replace crystal oscillators in almost any electronic system. The user can configure the device to produce nearly any output frequency from any input frequency by grounding or floating the select pins. Neither microcontroller, software, nor device programmer are needed to set the frequency. Using Phase-Locked Loop (PLL) techniques, the device accepts a PECL clock to produce output clocks up to 250 MHz, keeping them frequency locked together. Resistors are for PECL outputs only. For simple multipliers to produce common frequencies, refer to the Loco™ family of parts, which are smaller and more cost effective. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed.