Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | SOIC |
| Pkg. Code: | DCG8 |
| Lead Count (#): | 8 |
| Pkg. Dimensions (mm): | 4.9 x 3.9 x 1.5 |
| Pitch (mm): | 1.27 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 8 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 3000 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Advanced Features | Programmable Clock, Spread Spectrum, Reference Output |
| Core Voltage (V) | 3.3 |
| Family Name | VersaClock |
| Input Freq (MHz) | 50 |
| Input Type | Crystal, LVCMOS |
| Inputs (#) | 1 |
| Length (mm) | 4.9 |
| MOQ | 3000 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 0.25 - 200 |
| Output Type | LVCMOS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 2 |
| Package Area (mm²) | 19.1 |
| Period Jitter Typ P-P (ps) | 200 |
| Phase Jitter Typ RMS (fs) | 50000 |
| Phase Jitter Typ RMS (ps) | 50 |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 4.9 x 3.9 x 1.5 |
| Pkg. Type | SOIC |
| Prog. Clock | Yes |
| Prog. Interface | OTP |
| Published | No |
| Reel Size (in) | 13 |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Tape & Reel | Yes |
| Thickness (mm) | 1.5 |
| Width (mm) | 3.9 |
Resources for 342
Description
The 342 is a low cost, dual-output, field programmable clock synthesizer. The 342 can generate two output frequencies from 250 kHz to 200 MHz, using up to two independently configurable PLLs. The outputs may employ Spread Spectrum techniques to reduce system electro-magnetic interference (EMI). Using ICS' VersaClockTM software to configure the PLL and output, the 342 contains a One-Time Programmable (OTP) ROM to allow field programmability. Programming features include 2 selectable configuration registers. Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. The device also has a power down feature that tri-states the clock outputs and turns off the PLLs when the PDTS pin is taken low. The 342 is also available in factory programmed custom versions for high-volume applications.