Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | SOIC |
| Pkg. Code: | PSG24 |
| Lead Count (#): | 24 |
| Pkg. Dimensions (mm): | 15.4 x 7.6 x 2.34 |
| Pitch (mm): | 1.27 |
Environmental & Export Classifications
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 1 |
Product Attributes
| Pkg. Type | SOIC |
| Lead Count (#) | 24 |
| Pb (Lead) Free | Yes |
| Carrier Type | Reel |
| Advanced Features | Programmable Clock, Feedback Input |
| Core Voltage (V) | 3.3 |
| Feedback Input | Yes |
| Input Freq (MHz) | 0.008 - 100 |
| Input Type | LVCMOS |
| Inputs (#) | 2 |
| Length (mm) | 15.4 |
| MOQ | 1000 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Banks (#) | 5 |
| Output Freq Range (MHz) | 250 |
| Output Type | LVPECL, SSTL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 5 |
| Package Area (mm²) | 117 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 15.4 x 7.6 x 2.34 |
| Prog. Clock | Yes |
| Prog. Interface | I2C |
| Published | No |
| Qty. per Carrier (#) | 0 |
| Qty. per Reel (#) | 1000 |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | Yes |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 2.34 |
| Width (mm) | 7.6 |
Resources for 1524A
Description
The 1524A is a low-cost, very high-performance frequency generator and phase controlled clock synthesizer. It is perfectly suited to phase controlled clock synthesis and distribution as well as line-locked and genlocked applications. The 1524A offers two channels of clock phase controlled outputs; CLK and DPACLK. These two output channels have both 250 MHz PECL differential and 150 MHz SSTL_3 single-ended output pins. The CLK output channel has a fixed phase relationship to the PLL's input and the DPACLK uses the Dynamic Phase Adjust circuitry to allow control of the clock phase relative to input signal. Optionally, the CLK outputs can operate at half the clock rate and phase aligned with the DPACLK channel, enabling deMUXing of multiplexed analog-to-digital converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output or a re-synchronized and sharpened input HSYNC. The advanced PLL uses either its internal programmable feedback divider or an external divider and is programmed by a standard I2C-bus™ serial interface.