Flash A/D Converter Technology with Ultra High Speed and Low Power Consumption Is Produced with a 90nm Process

2007 Symposium on VLSI Circuits Paper Session 7-2 detailed a 6-bit A/D converter built with proprietary circuit technology that achieves 3.5G samples/second performance, yet operates on only 98mW

Renesas has developed an advanced analog-to-digital (A/D) converter that delivers the fast speed and low power consumption required in applications such as optical and UWB communications circuits and the read/write circuits of optical and hard disk drives (ODDs and HDDs). The new data converter uses a flash-type conversion approach and has been built in circuit technology developed for the 90nm CMOS process. Tests of the chip show that even when the supply voltage is reduced to 0.9V, the A/D makes reliable data conversions at very high speeds.

Applications such as optical and UWB communication circuits, as well as the read/write circuits in ODDs and HDDs, require ultra-high-speed A/D converters that can achieve sampling speeds in excess of 1G samples/second with 6-bit or 7-bit resolution. Moreover, the A/D circuits have to operate reliably low power consumption. Different methods are available for implementing A/D conversion, but Renesas uses flash conversion because it meets both requirements. "Especially, we believe that flash conversion is the most amenable to increasing the speed with which conversions are performed," said Mr. Deguchi.

In a flash-type A/D, the analog input signal is amplified in parallel preamps and then converted to the digital signal in a larger set of parallel comparators (see Figure 1). This method is also called parallel conversion because the conversion of all the bits is performed simultaneously. Although this type of signal processing is fast, it has a major disadvantage: the footprint (chip area) of the circuit and its power consumption increase with higher resolution. This is because a flash A/D with N-bit resolution requires a minimum of "two to the power of N minus one" (2 ^N -1) comparators. For example, to obtain a resolution of 6 bits, the flash A/D circuit must use at least 63 comparators.

The Renesas engineers used a comparatively fine 90nm CMOS process to produce the newly developed flash A/D converter. This allowed the circuit to be implemented with a small circuit footprint and low power consumption. However, the 90nm process has a lower limit for power supply voltage of only 0.9V. This limitation made it difficult to achieve the requisite high-speed operation

The challenge for the R&D team, then, was to invent technology for increasing the speed of the preamp and comparator circuits. Their solution involved adding a duplicate amplifier circuit, called a "replica circuit," to the latter stage of the preamp, and also using feedback from the output voltage to adjust the gate voltage of the load transistor in the actual amplifier circuit (see Figure 2). This circuit design approach enables the A/D to perform fast conversions even when the supply voltage is low. A single replica circuit can be used to control the gate voltage of all of the converter's other amplifiers. Therefore, it requires a negligible increase in circuit footprint and has little effect on the converter's total power consumption.

A key design issue for the comparator circuit was to determine how to speed up the change in output when the input signal was going from a large positive polarity input to a small negative polarity input, a condition called “overdrive recovery”. The newly developed circuit (see Figure 3) uses two MOS-type capacitors to achieve this output-change acceleration; that is, the charge in the capacitors increases the rate at which the output voltage changes. The engineers used a circuit simulator to determine the optimum value for the acceleration capacitors.

A prototype A/D converter manufactured in the 90nm process had a footprint of 330?m x 450?m (Figure 4 shows the layout). When the chip was tested, the converter demonstrated extremely good characteristics (see Table 1). "Compared to results published in the literature by competitors, the characteristics we obtained were outstanding," commented Mr. Deguchi. In particular, the power efficiency that the Renesas engineers recorded was the best ever achieved for a 6-bit A/D converter capable of performing more than 1G samples/second (see figure of merit [FOM] in Table 2). The circuit's operation consumes only 98mW.

The new A/D technology is attracting attention as a way to increase the speed and decrease the power consumption of the ODDs, HDDs, and similar devices used in digital data terminals, PCs, and elsewhere.