Built with a proprietary memory-cell technology that uses a stacked-capacitor structure, R1LV3216R- and R1WV6416R-series LPSRAMs are highly reliable and free from soft errors

The extensive experience Renesas has acquired manufacturing low-power SRAM (LPSRAM) devices for many years benefits two groups of new products: 32Mbit models with a small chip size, and a 64Mbit devices that stack two 32Mbit chips to offer the largest capacity of any such product. The chips are based on a Renesas-developed memory cell technology that provides both compact size and immunity to soft errors. Available in a variety of specifications and in a range of packages, these LPSRAMs are ideal for applications such as industrial systems, business equipment, consumer products, automotive systems, and communications gear.

Renesas low-power SRAMs are widely used for battery-backed data and image storage, microcomputer work memory, and graphics processor buffer memory in all sorts of embedded systems in industrial, business, consumer, automotive, and communications markets, among others. In these vibrant markets, three trends have emerged. First, systems are requiring more SRAM capacity as features are added and capabilities expanded. Second, engineers have begun to replace synchronous DRAM (SDRAM) with large-capacity low-power SRAM (LPSRAM) to avoid design and manufacturing disruptions caused by the relatively rapid procession of successive generations of SDRAMs. Third, LPSRAM chips don't require data refreshes, so they consume less power than pseudo SRAM (PSRAM) devices, which use SDRAM or DRAM memory cells as the SRAM interface. This makes LPSRAMs advantageous for applications that use batteries for data backup.

In response to these trends, semiconductor manufacturers are working to develop larger capacity LPSRAMs, traditionally through the use of greater process miniaturization. However, this straightforward design approach is inherently problematic because greater levels of miniaturization have a tendency to increase the soft-error rate (SER). Problems arise because miniaturization reduces the capacitance of the memory cells, making it easier for the cell's flip-flop logic circuit to erroneously change state when subjected to the unavoidable, unpredictable electrical disturbances caused by alpha particles or high-energy neutrons penetrating the silicon substrate. Obviously, data errors can adversely affect system operation and should be eliminated from SRAM operation.

In this regard, Renesas has a distinct advantage in SRAM technology. We have developed a proprietary memory cell design that delivers low SERs and accommodates miniaturization. Our unique technology applies a technique well proven in DRAM cells: a stacked capacitor configuration for the memory nodes that allows a small memory cell surface area, while also preventing capacitance reduction due to process miniaturization, thereby eliminating soft errors. Specifically, for the requisite P-channel load transistors, our SRAM cell uses polysilicon thin-film transistors (TFTs) formed in a layer above the cell's other transistors. We first incorporated this technology into the Advanced LPSRAM product line launched in 2003 ? devices that are soft-error free.

The Renesas SRAM cell technology also provides another important benefit. All the circuit elements underneath the TFTs ? the driver and access transistors ? are N-channel components. Therefore, there is no danger that they can form parasitic thyristor (PNPN) configurations that can cause unwanted current flow. As a result, cell latchups cannot occur in theory, so SRAM reliability is increased.

Our Advanced LPSRAMs currently in full-scale production are 4Mbit, 16Mbit and 32Mbit devices, the latter consisting of two 16Mbit chips in a single package. Now joining them to meet market demand are 20 new LPSRAMs built with a 0.15?m CMOS process: eight 32Mbit (single-chip) devices in the R1LV3216R series and twelve higher-capacity 64Mbit models in the R1WV6416R series. They encompass versions with 55ns or 70ns access times that come in a range of packages (see Table).

With this product-line expansion, Renesas now offers more than 100 SRAM design choices from 256Kbits to 64Mbits. Devices include Advanced LPSRAM products that incorporate our proprietary technology, as well as others with conventional memory cell configurations.

Devices the 64Mbit R1WV6416R series meet demands for larger-capacity low-power SRAM for high-performance systems, saving valuable board space by replacing two 32Mbit or four 16Mbit devices. They achieve their 64Mbit capacity ? the most of any LPSRAM currently available ? by stacking two 32Mbit Advanced LPSRAMs in a single package. Those R1LV3216R series chips are smaller than any other manufacturers' low-power SRAMs with 32Mbit capacities.

The Advanced LPSRAMs in both the R1LV3216R and R1WV6416R series are available in versions with 48-pin TSOP-I and 52-pin ?TSOP packages. The 64Mbit model is also available in a 48-ball FBGA package. The TSOP-I versions use the same package as the 16Mbit Advanced LPSRAMs and our conventional memory cell devices, and the ?TSOP versions use the same package across the 8Mbit, 16Mbit, 32Mbit, and 64Mbit sizes. Similarly, the FBGA packages are upwardly compatible. The same ball layout is used for the 4Mbit, 8Mbit, 16Mbit, 32Mbit, and 64Mbit SRAMs. This consistency within the product line provides valuable system design flexibility. Engineers can add data storage just by inserting a higher-capacity SRAM into the circuit board, without modifying the board's layout.

Renesas' future plans for SRAM products include Advanced LPSRAMs that meet the stringent specifications mandated by automotive applications. We also aim to offer total solutions that combine automotive-grade memory and microcomputers.