New 4Mbit and 16Mbit SRAMs Use Tiny WL-CSP Packages to Boost Mounting Density in Portable Equipment

The new Renesas advanced low-power SRAMs combine both miniaturization and reliability. Packaged in ultra-small wafer-level chip-size packages (CSPs), they need up to 75-percent less mounting area than previous models, helping customers to achieve ultra-high component density in small portable equipment. Two versions are available, the 16Mbit R1LV1616RBA SRAM and the 4Mbit R1LV0416DBA version.

There are two types of static RAM (SRAM): the ultra-fast SRAMs used for data buffers in servers and network equipment, and the low- power types used for data storage in battery-operated products such as digital video cameras (DVCs) and mobile phones. Renesas supplies low- power types and sees strong customer requirements for new versions that consume less power and occupy less space.

To address these requirements, we had previously developed the Advanced Low Power SRAM (A-LP SRAM), which combines both small size and low power consumption. We had also established a product range using the fine-pitch ball grid array (FBGA) package, a standard package type for small components. Yet the trend to greater functionality and smaller size in portable consumer equipment has created demand for even smaller versions of the components used in such products. This has spurred us to achieve higher levels of miniaturization in low-power SRAMs.

Renesas' success is demonstrated by the ability to package A-LP SRAM chips in wafer-level chip-size packages (WL-CSPs), which are even smaller than FBGAs. The first miniaturized SRAMs to offer this size-shrinking packaging technology are the 4Mbit R1LV0416DBA and the 16Mbit R1LV1616RBA (see Photograph). They have 55ns and 70ns access times, respectively, and their standby currents are 1μA and 2μA, respectively (typical values).

The external dimensions of the 4Mbit SRAM are only 3.55mm x 4.45mm, while the slightly larger 16Mbit device measures 5.62mm x 5.82mm. Both devices are significantly smaller than previous models (see Figure). Compared to previous FBGA versions, the new type of package has succeeded in reducing the mounting footprints by 75 percent for the 4Mb version and 49 percent for the 16Mbit version. Moreover, the new packages are thinner than the FPGA versions. The height of the 4Mb device has been reduced to 0.74mm and the 16Mbit version is only 0.79mm high (see Table).

These smaller and slimmer packages make it easier for customers to obtain ultra-high mounting densities in mobile phone modules (cameras, one-segment tuners, etc.), as well as in small portable products such as DVCs.

Not only has the Renesas A-LP SRAM fabrication technology reduced power consumption by adopting polysilicon thin-film transistors (TFTs) as the internal load transistors, it has also shrunk the chip size by approximately half compared with past devices. In terms of process design rules, this is equivalent to two generations of miniaturization.

The A-LP SRAM memory cell is designed for improved reliability. Its structure eliminates the possibility of latch-up by preventing the formation of parasitic transistors. Also, it incorporates a capacitor that solves the problem of the soft errors that was a fundamental weakness of past SRAM designs. Other detailed enhancements that have been made to achieve JEDEC Level 2 reliability include a technique for obtaining superior tolerance for moisture absorption during reflow and another for improving mounting reliability through optimization of the solder ball height.

Renesas plans to extend its range of low-power SRAMs based on this newly developed technology by adding versions with different memory sizes.