Easy-to-use architecture for embedded systems uses two SH-2A CPU cores to deliver up to 960 MIPS while keeping power consumption low

Renesas has been developing multi-core versions of its SuperH high-end microcomputers for two main reasons: to meet increasing demand for advanced digital processing functions such as video, and to avoid the higher power consumption that results when faster microcomputer operating speeds are used to satisfy these demands. The SH2A-DUAL controller-oriented microcomputer architecture incorporates two SH2A-FPU CPU cores in a configuration that achieves outstanding performance while consuming relatively low amounts of power. The new SH7205 and SH7265 microcontrollers incorporate this new architecture and give customers impressive new system design capabilities that can open untapped market opportunities.

The 32-bit SH2A-FPU CPU has a superscalar SuperH configuration, Harvard architecture, on-chip floating point unit (FPU), and parallel flash access. Previously it was Renesas' highest-performance controller-oriented microcomputer core, delivering an impressive processing performance of 480MIPS when running at 200MHz. Nevertheless, customers now need even more performance to handle digital processing functions such as video. Obtaining that performance by increasing the core's operating speed would raise power consumption to levels unacceptably high for embedded systems. Instead, the Renesas solution is the innovative "SH2A-DUAL" CPU core, which incorporates two SH2A-FPU cores in a multi-core design with a carefully engineered, optimized configuration. The new core achieves up to 960-MIPS (million instructions per second) /800-MFLOPS (mega floating point number operations per second) high-speed processing on a single chip, marking it a true next-generation core. It is used in the recently announced SH7205 microcontroller (see Figure 1) and SH7265 microcontroller.

The SH2A-DUAL CPU core provides important advantages. It shares bus, memory, and other resources, so the cost and circuit board footprint of the microcontrollers that use it are much less than the equivalent for two separate devices. The new devices achieve double the processing performance of devices with the SH2A-FPU CPU core, without a commensurate jump in power consumption. With this solution, real-time processing does not degrade as processing becomes more complex and faster.

Each of the two SH2A-FPU CPUs in the SH2A-DUAL CPU core includes a CPU, FPU, instruction cache, data cache, and an on chip high-speed RAM (URAM). Inter-CPU synchronization and direct CPU-to-CPU communication is performed using interrupt processing. Each CPU can check the status of the other one, send interrupts to it, and exchange data using memory provided for that purpose. Thus, processing linkage can be implemented between the CPUs through mutual exchanges of their respective processing states and data. Support for exclusive control (semaphore control) is implemented using registers located out side of the two CPUs.

A four-layer bus configuration is used. The 32-bit multi-layer bus (MLB) is designed with an emphasis on latency performance. Two layers are for CPU use, one for each CPU. The other two are for DMAC (direct memory access controller) use. This arrangement prevents delays when a bus is being used by a CPU for high-speed real-time processing. The four-layer bus configuration is well proven, being already in wide use as the standard bus in Renesas SoC devices.

Renesas is aware that users might have concerns about multi-core devices. They may perceive that such chips are difficult to use and could cause problems in system development. For that reason Renesas has, since the inception of the SH2A-DUAL development program, actively sought user inputs on ways to make multi-core microcontrollers easy to use in embedded applications. We have also focused on creating an architecture that offers design flexibility. As a result, the architecture has emerged as a multi-core microcontroller solution oriented towards distributed-function configurations.

When multi-core devices are used for embedded applications, there appears to be little demand for distributed execution of the same processing. Instead, the predominant use of the technology will be to execute different processing on different cores. In one typical type of application for a microcontroller with the SH2A-DUAL architecture, one core will be used as a standard CPU running an operating system (OS), while the other core is used as an accelerator without an OS. In another typical type of application, the same OS will run on both cores. In a third type of application, a heterogeneous configuration will be used in which each of the cores runs a different OS (see Figure 2).

To help customers apply microcontrollers with the SH2A-DUAL architecture in such configurations and in designs that achieve the devices' performance potential, Renesas offers various support tools. For example, development systems allow engineers to make use of application resources and CPU and RAM combinations that we have accumulated through our product development activities. Currently available compiler, assembler, and linker products can be used as a system development environment. Additional tools include a multi-core OS designed for embedded applications (Dual-ITRON) and a dedicated debugger.

Microcontrollers that use the SH2A-DUAL CPU core will be members of the SH720x series. As previously mentioned, the first of these devices to be announced are the SH7205 and SH7265, which will be available in July 2007. These devices are basically the same, except that the SH7265 has a wider operating temperature range (-40 to +85 degree C) than the SH7205 (-20 to +85 degree C) and offers more on-chip functions. Their up to 960-MIPS/800-MFLOPS performance (at 200MHz), combined with the on-chip peripheral functions they provide, address the design requirements of many high-end consumer, industrial, automotive, and multimedia applications, among others. They are particularly well suited for systems that need both high-speed real-time control and processing performance equivalent to that of a digital signal processor (DSP) chip.

Each of the devices' SH2A-FPU cores has cache size of 8Kbytes. There are 64Kbytes of URAM on CPU0 (the primary CPU) and 32Kbytes on CPU1 (the secondary CPU). In a typical application, CPU0 might provide system control, while CPU1 handles tasks such as motor control or communication control.

To reduce the need for external parts and lower the overall system cost, the SH7205 and SH7265 microcontrollers provide a USB v2.0 High-Speed (480-Mbps) interface, an ATAPI interface, and others. They also offer a 2D graphic engine and a digital video input pin for graphic processing, and WQVGA-size (480x234-pixel) and QVGA-size (320x240-pixel) analog RGB output pins for image and video output processing. Additional on-chip functions include a 5-channel multifunction timer unit (MTU2) suitable for motor control systems, 2-channel CAN controller, 8-channel 10-bit A/D converter, 2-channel 8-bit D/A converter, watchdog timer (WDT), and 14-channel DMAC with 2-dimensional addressing capability for speeding up video applications. Besides those functions, SH7265 models include an AAC encoder accelerator, an IE Bus controller, and an SD memory card interface.

The SH7205 and SH7265 microcontrollers are designed with features that allow tight control over power consumption. They have four separate clocks: independent 200MHz (max.) clocks for CPU0 and CPU1, a 66MHz (max.) clock for the bus, and a 33MHz (max.) clock for the peripheral functions. Moreover, six power-down modes are available: dual-processor mode, single-processor mode, dual-sleep mode, standby mode, deep-standby mode, and module-standby mode. The first three of these are new modes that independently control the power supply to each SH2A-FPU CPU.

Rather than having separate debug pins, both cores in the SH7205 and SH7265 chips share a single debug module. The multi-core debugger connects using the same H-UDI port connector that has been used in the past.