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Network Memory
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Overview
Renesas offers memory products for packet relay/transfer suited to network equipment (router/switch, etc.) that require high-speed processing of large-capacity data. Renesas memory products allow systems to be developed easily.
QDR-SRAM
QDR™ (Quad Data Rate) SRAMs are the ideal devices for next-generation communications applications.
Network SRAMThe Network SRAM is a ZBT™ (Zero Bus Turnaround™ (ZBT®) *1) compatible, 18 Mb device within an industry standard package.
TCAMTCAM is a type of memory in which each memory cell can store three data states: 0, 1, and X ("Don't Care"). It is suitable for applications such as networking equipment, because it achieves high-speed searches by using simultaneous parallel operation to compare data strings.
System Block Diagram
Recommended products
QDR™-II / DDR-II SRAM Lineup
| Density (bits) |
36 M / 72 M
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| Type |
QDR™-II
|
DDR-II
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| Function |
2-word burst
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4-word burst
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2-word burst (SIO/CIO)
|
4-word burst (CIO)
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| Power supply voltage | VDD |
1.7 V to 1.9 V
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| VDDQ |
1.4 V to VDD
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| Interface |
HSTL
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| Bit configuration |
x9 / x18 / x36
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| Latency |
1.5
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| Operating frequency (MHz) |
167 / 200 / 250
|
200 / 250 / 300 / 333
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| Transfer rate (Mbps) |
333 / 400 / 500
|
400 / 500 / 600 / 666
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| Cycle time (ns) |
6.0 / 5.0 / 4.0
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5.0 / 4.0 / 3.3 / 3.0
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| JTAG |
Limited function of IEEE1149.1
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| Package |
165-ball MAP-BGA (15 x 17 mm)
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QDR™-II+ / DDR-II+ SRAM Lineup
| Density (bits) |
72 M
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| Type |
QDR™-II+
|
DDR-II+
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| Function |
4-word burst
|
2-word burst (SIO/CIO)
|
4-word burst (CIO)
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| Power supply voltage |
VDD |
1.7 V to 1.9 V
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| VDDQ |
1.4 V to VDD
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| Interface |
HSTL
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| Bit configuration |
x9 / x18 / x36
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| Latency |
2.0 or 2.5
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| Operating frequency (MHz) |
300 / 333 / 375 / 400 / 450 / 500 / 533
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| Transfer rate (Mbps) |
600 / 666 / 750 / 800 / 900 / 1000 / 1066
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| Cycle time (ns) |
3.3 / 3.0 / 2.7 / 2.5 / 2.2 / 2.0 / 1.9
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| JTAG |
Limited function of IEEE1149.1
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| Package |
165-ball MAP-BGA (15 mm x 17 mm)
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| On-die termination |
The device incorporates an input termination resistor. The input termination resistance value can be adjusted by the user by means of an RQ connected to the ZQ pin. (Selected by ODT pin) 105 < Rtt < 150 or 52 < Rtt < 105
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Network SRAM Lineup
| Density (bits) |
18 M
|
|
| Part no. |
M5M5V5A36GP
|
M5M5V5636GP
|
| Bit configuration |
512 K x 36
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| Package |
100-pin TQFP (16 mm x 22 mm)
|
100-pin TQFP (16 mm x 22 mm)
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| Power supply voltage |
3.3 V
|
3.3 V / 2.5 V
|
| Operating frequency |
100 MHz (8.5ns clock access time)
|
167 MHz
|
| Function |
Late write and flow-through read
|
Double late write and pipeline read
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